Cover Page

Series Editor
Robert Baptist

Simulation of Transport in Nanodevices

Edited by

François Triozon

Philippe Dollfus

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Preface

This book gives an overview of the various methods used to simulate electronic transport in nanoelectronics devices. The miniaturization of transistors to sizes below 20 nm, together with the increasing variety of materials involved in these devices, leads to new challenges for simulation. Quantum mechanical effects are enhanced at such small length scales. Moreover, simulations at the atomic scale are needed to obtain an accurate description of new materials and of their interfaces and defects. Predicting the performances of next generation devices hence requires a multi-scale simulation strategy, from the simulation of materials at the atomic scale to the simulation of electron and heat transport at the device and even circuit scale.

In this book, we focus on the simulation of electronic transport at the device level. In Chapter 1, the field of nanoelectronics is briefly presented and basic notions of solid state physics and of electronic transport are introduced. This chapter serves as an introduction to the other chapters of the book, which are much more specialized and detailed. Before examining the various simulation methods, it is first necessary to introduce some theoretical background concerning solid state physics and the simulation and modelling of materials at the atomic scale. This is the purpose of Chapters 2, 3 and 4. The other chapters then present different methods for the simulation of electronic transport, based on quantum mechanical or semi-classical formalisms.

The book is mainly intended for Master’s or PhD students beginning a research project in nanoelectronics.

François TRIOZON
Philippe DOLLFUS
September 2016

List of Symbols

e, q elementary charge
h Planck constant
ħ reduced Planck constant (= h/2π)
kB Boltzmann constant
ψ, ϕ, φ, χ wavefunction
H Hamiltonian
V, U potential energy
m0 electron mass
m, m* effective mass
E, ε energy
k electron wavevector
q phonon wavevector
p linear momentum
ω angular frequency
v(k) group velocity
f(E) Fermi-Dirac distribution
E, Ɛ electric field
B magnetic field
T temperature
n carrier density
ρ density matrix
G, Gr, Ga, G<, G> Green’s functions
j(E) spectral current density
A(E) spectral function
Σ self-energy
ck+, ck, ψ(r)+, ψ(r) electron creation and annihilation operators
aq+, aq phonon creation and annihilation operators
fb Boltzmann distribution function
fw Wigner function
Vw Wigner potential
Ds density of states
si(k,k') scattering rate from state k to state k'
Γi(k,k') scattering rate from state k to any final state
image(k,k') overlap integral
image(k,k') overlap factor

List of Abbreviations

CMOS Complementary Metal-Oxide-Semiconductor
MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
SPICE Simulation Program with Integrated Circuit Emphasis
AC Alternating Current
DC Direct Current
BTE Boltzmann Transport Equation
WTE Wigner Transport Equation
DFT Density Functional Theory
MC Monte Carlo
LDA Local Density Approximation
GGA Generalized Gradient Approximation
FDSOI Fully-Depleted Silicon On Insulator
EPM Empirical Pseudopotential Method
CB Conduction Band
VB Valence Band
TB Tight-Binding
LCAO Linear Combinations of Atomic Orbitals
SCBA Self-Consistent Born Approximation
ITRS International Technology Roadmap for Semiconductors
DM Density Matrix
GW Commonly used approximation for many-body effects. G is the Green’s functions and W the screened Coulomb potential
MD Molecular Dynamics
RTA Relaxation Time Approximation
BZ Brillouin Zone
PES Potential Energy Surface
DOS Density of States

1
Introduction: Nanoelectronics, Quantum Mechanics, and Solid State Physics

1.1. Nanoelectronics

1.1.1. Evolution of complementary metal–oxide–semiconductor microelectronics toward the nanometer scale

Current microprocessors are based on the complementary metal–oxide–semi-conductor (CMOS) technology, whose main building blocks are field-effect transistors (MOSFETs). A transistor is made of a semiconducting silicon “channel” connected to “source” and “drain” electrodes. The electrical current through the channel is controlled by a voltage applied to a third electrode, called the “gate” electrode, separated from the channel by a thin insulating layer. Figure 1.1 shows transmission electron microscopy images of MOSFETs. During the past decades, the microelectronics industry has constantly reduced the size of transistors in order to increase the complexity and speed of microprocessors. Current transistors have a channel length LG of the order of 20 nm, and a channel thickness below 10 nm. Such length scales are close to the typical wavelength of the electrons’ wavefunctions propagating through the channel, which enhances quantum effects. The main quantum and atomistic effects occurring in CMOS technology are summarized in Table 1.1.

image

Figure 1.1. Transmission electron microscopy cross-sections of MOSFETs. Left panel: longitudinal cross-section of a fully-depleted silicon-on-insulator (FDSOI) transistor [LIU 13]. The channel is made of a thin silicon film lying on an oxide layer. Right panel: transverse cross-section of an ‘Ω-gate’ transistor. The channel is made up of a SiGe nanowire with a diameter of 12 nm [NGU 14]

Table 1.1. Phenomena occurring at different transistor gate lengths LG

LG > 100 nm “Classical” microelectronics
10 nm < LG < 100 nm Quantization of energy levels in the channel Gate leakage by tunneling through the thin oxide Small and uncontrolled number of impurities
LG < 10 nm Wave phenomena along the transport direction Few electrons in the channel

When decreasing the gate length, the thickness of the silicon oxide (SiO2) layer separating the gate electrode from the channel must be reduced accordingly in order to keep a good electrostatic control of conduction inside the channel. However, reducing the SiO2 thickness below 2 nm leads to detrimental current leakage through the oxide. Hence, materials with higher dielectric constant, such as HfO2, have been introduced. They allow for a good electrostatic control with larger oxide thickness, hence limiting gate leakage. The transistors shown in Figure 1.1 feature such high-κ gate stacks. This is a first example of a new material introduced in nanoelectronics devices. Other examples are SiGe alloys, used in “p-type” transistors (see the right panel in Figure 1.1) to improve the “hole” mobility, and silicidation of silicon in the source and drain regions to reduce the electrical resistance between the metal contacts and the transistor.

1.1.2. Post-CMOS nanoelectronics

While the quantum effects occurring at the nanometer scale tend to limit the performance of CMOS devices, they can be exploited to develop novel types of devices. This is the purpose of post-CMOS nanoelectronics, a research field that has grown considerably during the last two decades. Figure 1.2 shows a tentative classification of these phenomena.

image

Figure 1.2. Tentative classification of quantum phenomena that can be exploited in nanoelectronics

Figures 1.3 shows examples of post-CMOS devices exploiting the wave nature of the electron: a resonant tunneling diode [PAU 00] and a tunnel FET whose channel is made up of a carbon nanotube [APP 04]. Figure 1.4 shows devices exploiting the granularity of the charge: a “flash” memory with silicon nanocrystals [MOL 06] and a single electron transistor [LAV 15]. Such a variety of materials, nanostructures and quantum effects involved in nanoelectronics poses significant challenges to simulation.

1.1.3. Theory and simulation

From the very beginning, the development of transistors and microelectronics has been associated with theoretical progress in solid-state physics. Even the most basic properties of solids cannot be explained without quantum mechanics. In particular, their conducting or insulating properties are related to the wave nature of electrons [BLO 29, WIL 31]. Hence, a good knowledge of solid-state physics, including the quantum theory of solids, is needed to address the theory, simulation and modeling of electronic devices.

The mechanical and electronics properties of solids can be modeled at various degrees of refinement from the atomic scale to continuous medium models (see Chapters 2–4). Electronic transport can be described by an even broader variety of formalisms (Chapters 5–8). The semiclassical theory of electronic transport, which essentially consists of describing electron “wavepackets” as point particles (see Chapters 5 and 8), has successfully accompanied CMOS technology up to gate lengths well below 100 nm. Formalisms including the relevant quantum phenomena must be used for simulating smaller CMOS transistors and nanoelectronics devices.

image

Figure 1.3. Devices exploiting the wave nature of the electron. Left panel: resonant tunneling diode made up of a thin layer of silicon between two SiGe barriers [PAU 00]. Right panel: tunnel FET made up of a carbon nanotube channel controlled by an Al gate and a doped Si back gate [APP 04]

To study a given type of device, we have to choose a good approximation for modeling the electronic properties of the materials, and an appropriate formalism for simulating electronic transport. This requires a good knowledge of the available formalisms and how they capture the quantum phenomena involved in the device operation. The main purpose of this book is to give an overview of some commonly used formalisms for electronic transport.