Details

FPGA Prototyping by SystemVerilog Examples


FPGA Prototyping by SystemVerilog Examples

Xilinx MicroBlaze MCS SoC Edition
2. Aufl.

von: Pong P. Chu

84,99 €

Verlag: Wiley
Format: PDF
Veröffentl.: 18.04.2018
ISBN/EAN: 9781119282693
Sprache: englisch
Anzahl Seiten: 656

DRM-geschütztes eBook, Sie benötigen z.B. Adobe Digital Editions und eine Adobe ID zum Lesen.

Beschreibungen

<p><b>A hands-on introduction to FPGA prototyping and SoC design</b></p> <p>This is the successor edition of the popular <i>FPGA Prototyping by Verilog Examples</i> text. It follows the same “learning-by-doing” approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems.</p> <p>The book is completely updated and uses the SystemVerilog language, which “absorbs” the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The new edition:</p> <ul> <li>Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I<sup>2</sup>C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.</li> <li>Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.</li> <li>Expands the original video controller into a complete stream based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.</li> <li>Provides a detailed discussion on blocking and nonblocking statements and coding styles.</li> <li>Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.</li> <li>Provides an overview of bus interconnect and interface circuit.</li> <li>Presents basic embedded system software development.</li> <li>Suggests additional modules and peripherals for interesting and challenging projects.</li> </ul> <p><i>FPGA Prototyping by SystemVerilog Examples</i> makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.</p>
<p>Preface xxvii</p> <p>Acknowledgments xxxiii</p> <p><b>PART I BASIC DIGITAL CIRCUITS DEVELOPMENT</b></p> <p><b>1 Gate-Level Combinational Circuit 1</b></p> <p>1.1 Introduction 1</p> <p>1.1.1 Brief history of Verilog and SystemVerilog 1</p> <p>1.1.2 Book coverage 2</p> <p>1.2 General description 3</p> <p>1.3 Basic lexical elements and data types 4</p> <p>1.3.1 Lexical elements 4</p> <p>1.3.2 Data types used in the book 5</p> <p>1.3.3 Number representation 6</p> <p>1.3.4 Operators 7</p> <p>1.4 Program skeleton 7</p> <p>1.4.1 Port declaration 7</p> <p>1.4.2 Signal declaration 8</p> <p>1.4.3 Program body 8</p> <p>1.4.4 Concurrent semantics 9</p> <p>1.4.5 Another example 10</p> <p>1.5 Structural description 10</p> <p>1.6 Top-level signal mapping 13</p> <p>1.7 Testbench 14</p> <p>1.8 Bibliographic notes 16</p> <p>1.9 Suggested experiments 16</p> <p>1.9.1 Code for gate-level greater-than circuit 17</p> <p>1.9.2 Code for gate-level binary decoder 17</p> <p><b>2 Overview of FPGA and EDA Software 19</b></p> <p>2.1 FPGA 19</p> <p>2.1.1 Overview of a general FPGA device 19</p> <p>2.1.2 Overview of the Xilinx Artix-7 devices 20</p> <p>2.2 Overview of the Digilent Nexys 4 DDR board 21</p> <p>2.3 Development flow 22</p> <p>2.4 Xilinx Vivado Design Suite 24</p> <p>2.5 Bibliographic notes 24</p> <p>2.6 Suggested experiments 24</p> <p>2.6.1 Gate-level greater-than circuit 24</p> <p>2.6.2 Gate-level binary decoder 26</p> <p><b>3 RT-Level Combinational Circuit 29</b></p> <p>3.1 Operators 29</p> <p>3.1.1 Arithmetic operators 31</p> <p>3.1.2 Shift operators 31</p> <p>3.1.3 Relational and equality operators 32</p> <p>3.1.4 Bitwise, reduction, and logical operators 32</p> <p>3.1.5 Concatenation and replication operators 33</p> <p>3.1.6 Conditional operators 34</p> <p>3.1.7 Operator precedence 35</p> <p>3.1.8 Expression bit-length adjustment 35</p> <p>3.1.9 Synthesis of z and x values 36</p> <p>3.2 Always block for a combinational circuit 38</p> <p>3.2.1 Overview of always block 39</p> <p>3.2.2 Procedural assignment 40</p> <p>3.2.3 Conceptual examples 40</p> <p>3.3 Coding guidelines 43</p> <p>3.4 If statement 43</p> <p>3.4.1 Syntax 43</p> <p>3.4.2 Examples 44</p> <p>3.5 Case statement 45</p> <p>3.5.1 Syntax 45</p> <p>3.5.2 Examples 46</p> <p>3.5.3 The casez and casex statements 47</p> <p>3.5.4 Full case and parallel case 48</p> <p>3.6 Routing structure of conditional control constructs 49</p> <p>3.6.1 Priority routing network 49</p> <p>3.6.2 Multiplexing network 51</p> <p>3.7 Additional coding guidelines for an always block 52</p> <p>3.7.1 Common errors in combinational circuit codes 52</p> <p>3.7.2 Guidelines 56</p> <p>3.8 Parameter and constant 56</p> <p>3.8.1 Constant 56</p> <p>3.8.2 Parameter 58</p> <p>3.9 Replicated structure 59</p> <p>3.9.1 Generate-for statement 59</p> <p>3.9.2 Procedural-for statement 60</p> <p>3.9.3 Example 60</p> <p>3.10 Design examples 62</p> <p>3.10.1 Hexadecimal digit to seven-segment LED decoder 62</p> <p>3.10.2 Sign-magnitude adder 65</p> <p>3.10.3 Barrel shifter 68</p> <p>3.10.4 Simplified floating-point adder 69</p> <p>3.11 Bibliographic notes 73</p> <p>3.12 Suggested experiments 73</p> <p>3.12.1 Multi-function barrel shifter 73</p> <p>3.12.2 Parameterized barrel shifter 74</p> <p>3.12.3 Dual-priority encoder 74</p> <p>3.12.4 BCD incrementor 74</p> <p>3.12.5 Floating-point greater-than circuit 74</p> <p>3.12.6 Floating-point and signed integer conversion circuit 74</p> <p>3.12.7 Enhanced floating-point adder 75</p> <p><b>4 Regular Sequential Circuit 77</b></p> <p>4.1 Introduction 77</p> <p>4.1.1 D FF and register 78</p> <p>4.1.2 Basic block system 78</p> <p>4.1.3 Code development 79</p> <p>4.1.4 Sequential circuit coding guidelines and style 79</p> <p>4.2 HDL code of the FF and register 80</p> <p>4.2.1 D FF 80</p> <p>4.2.2 Register 85</p> <p>4.3 Simple design examples 85</p> <p>4.3.1 Shift register 85</p> <p>4.3.2 Binary counter and variant 87</p> <p>4.4 Testbench for sequential circuits 89</p> <p>4.5 Case study 93</p> <p>4.5.1 LED time-multiplexing circuit 93</p> <p>4.5.2 Stopwatch 101</p> <p>4.6 Timing and clocking 104</p> <p>4.6.1 Timing of FF 104</p> <p>4.6.2 Maximum operating frequency 104</p> <p>4.6.3 Clock tree 107</p> <p>4.6.4 GALS system and CDC 107</p> <p>4.7 Bibliographic notes 108</p> <p>4.8 Suggested experiments 108</p> <p>4.8.1 Programmable square wave generator 108</p> <p>4.8.2 PWM and LED dimmer 108</p> <p>4.8.3 Rotating square circuit 109</p> <p>4.8.4 Heartbeat circuit 109</p> <p>4.8.5 Rotating LED banner circuit 109</p> <p>4.8.6 Enhanced stopwatch 110</p> <p><b>5 FSM 111</b></p> <p>5.1 Introduction 111</p> <p>5.1.1 Mealy and Moore outputs 112</p> <p>5.1.2 FSM representation 112</p> <p>5.2 FSM code development 115</p> <p>5.2.1 Enumerated data type and state assignment 115</p> <p>5.2.2 Multi-segment code 116</p> <p>5.2.3 Two-segment code 117</p> <p>5.3 Design examples 118</p> <p>5.3.1 Rising-edge detector 118</p> <p>5.3.2 Debouncing circuit 123</p> <p>5.3.3 Testing circuit 126</p> <p>5.4 Bibliographic notes 128</p> <p>5.5 Suggested experiments 128</p> <p>5.5.1 Dual-edge detector 128</p> <p>5.5.2 Early detection debouncing circuit 128</p> <p>5.5.3 Parking lot occupancy counter 129</p> <p><b>6 FSMD 131</b></p> <p>6.1 Introduction 131</p> <p>6.1.1 Single RT operation 132</p> <p>6.1.2 ASMD chart 132</p> <p>6.1.3 Decision box with a register 134</p> <p>6.2 Code development of an FSMD 137</p> <p>6.2.1 Debouncing circuit based on RT methodology 137</p> <p>6.2.2 Code with explicit data path components 137</p> <p>6.2.3 Code with implicit data path components 140</p> <p>6.2.4 Comparison 142</p> <p>6.3 Design examples 144</p> <p>6.3.1 Fibonacci number circuit 144</p> <p>6.3.2 Division circuit 147</p> <p>6.3.3 Binary-to-BCD conversion circuit 150</p> <p>6.3.4 Period counter 153</p> <p>6.3.5 Accurate low-frequency counter 156</p> <p>6.4 Bibliographic notes 159</p> <p>6.5 Suggested experiments 159</p> <p>6.5.1 Early detection debouncing circuit 159</p> <p>6.5.2 BCD-to-binary conversion circuit 160</p> <p>6.5.3 Fibonacci circuit with BCD I/O: design approach 1 160</p> <p>6.5.4 Fibonacci circuit with BCD I/O: design approach 2 160</p> <p>6.5.5 Auto-scaled low-frequency counter 161</p> <p>6.5.6 Reaction timer 161</p> <p>6.5.7 Babbage difference engine emulation circuit 162</p> <p><b>7 RAM and Buffer of FPGA 165</b></p> <p>7.1 Embedded memory of FPGA device 165</p> <p>7.1.1 Memory of an Artix device 166</p> <p>7.1.2 Memory available in the Nexys 4 DDR board 166</p> <p>7.2 General description for a RAM-like component 167</p> <p>7.2.1 Register file 167</p> <p>7.2.2 Dynamic array indexing operation 169</p> <p>7.2.3 Key aspects of a RAM module 170</p> <p>7.2.4 Genuine ROM 171</p> <p>7.3 FIFO buffer 173</p> <p>7.3.1 FIFO read configuration 174</p> <p>7.3.2 Circular queue implementation 175</p> <p>7.4 HDL templates for memory inference 178</p> <p>7.4.1 Methods to incorporate memory modules 178</p> <p>7.4.2 Synchronous dual-port RAM 179</p> <p>7.4.3 “Simple” synchronous dual-port RAM 180</p> <p>7.4.4 Synchronous single-port RAM 181</p> <p>7.4.5 Synchronous ROM 182</p> <p>7.4.6 BRAM-based FIFO buffer 183</p> <p>7.4.7 Design considerations 183</p> <p>7.5 Overview of memory controller 184</p> <p>7.6 Bibliographic notes 185</p> <p>7.7 Suggested experiments 186</p> <p>7.7.1 ROM-based sign-magnitude adder 186</p> <p>7.7.2 ROM-based temperature conversion 186</p> <p>7.7.3 FIFO with data width conversion 186</p> <p>7.7.4 Standard FIFO to FWFT FIFO conversion circuit 187</p> <p>7.7.5 FIFO buffer with extended status 187</p> <p>7.7.6 Stack 187</p> <p><b>8 Selected Topics of SystemVerilog 189</b></p> <p>8.1 Timing model 189</p> <p>8.1.1 Concurrent constructs 190</p> <p>8.1.2 Assignment statement 190</p> <p>8.1.3 Basic model 190</p> <p>8.1.4 Blocking versus nonblocking assignment 192</p> <p>8.2 Coding guidelines revisited 194</p> <p>8.2.1 “Single variable assignment” guideline 195</p> <p>8.2.2 “Blocking assignment for combinational circuit” guideline 195</p> <p>8.2.3 “Nonblocking assignment for register” guideline 197</p> <p>8.3 Alternative coding style 198</p> <p>8.3.1 First coding style revisited 198</p> <p>8.3.2 Sequential circuit with mixed blocking and nonblocking assignments 199</p> <p>8.3.3 Combined coding style 201</p> <p>8.3.4 Summary 206</p> <p>8.4 Data types 206</p> <p>8.4.1 The net and variable types 206</p> <p>8.4.2 The logic data type 207</p> <p>8.4.3 Limitation of the logic data type 208</p> <p>8.4.4 New data types in SystemVerilog 208</p> <p>8.5 Use of the signed data type 209</p> <p>8.5.1 Overview 209</p> <p>8.5.2 Signed number conversion 210</p> <p>8.6 Bibliographic notes 211</p> <p>8.7 Suggested experiments 211</p> <p>8.7.1 Shift register with blocking and nonblocking assignments 211</p> <p>8.7.2 Alternative coding style for the BCD counter 212</p> <p>8.7.3 Alternative coding style for the FIFO buffer 212</p> <p>8.7.4 Alternative coding style for the Fibonacci circuit 212</p> <p>8.7.5 Dual-mode comparator 212</p> <p><b>PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM</b></p> <p><b>9 Overview of Embedded SoC Systems 215</b></p> <p>9.1 Embedded SoC 215</p> <p>9.1.1 Overview of embedded systems 215</p> <p>9.1.2 FPGA-based SoC 216</p> <p>9.1.3 IP cores 216</p> <p>9.2 Development flow of the embedded SoC 217</p> <p>9.2.1 Hardware–software partition 217</p> <p>9.2.2 Hardware development flow 217</p> <p>9.2.3 Software development flow 219</p> <p>9.2.4 Physical implementation and test 219</p> <p>9.2.5 Custom IP core development 219</p> <p>9.3 FPro SoC Platform 220</p> <p>9.3.1 Motivations 220</p> <p>9.3.2 Platform hardware organization 221</p> <p>9.3.3 Platform software organization 223</p> <p>9.3.4 Modified development flow 224</p> <p>9.4 Adaptation on the Digilent Nexys 4 DDR board 224</p> <p>9.5 Portability 226</p> <p>9.5.1 Processor Module and Bridge 226</p> <p>9.5.2 MMIO subsystem 227</p> <p>9.5.3 Video subsystem 227</p> <p>9.6 Organization 228</p> <p>9.7 Bibliographic notes 228</p> <p><b>10 Bare Metal System Software Development 231</b></p> <p>10.1 Bare metal system development overview 231</p> <p>10.1.1 Desktop-like system versus bare metal system 231</p> <p>10.1.2 Basic embedded program architecture 232</p> <p>10.2 Memory-mapped I/O 233</p> <p>10.2.1 Overview 233</p> <p>10.2.2 Memory alignment 234</p> <p>10.2.3 I/O register map 234</p> <p>10.2.4 I/O address space of the FPro system 234</p> <p>10.3 Direct I/O Register Access 235</p> <p>10.3.1 Review of C pointer 235</p> <p>10.3.2 C pointer for I/O register 236</p> <p>10.4 Robust I/O register access 237</p> <p>10.4.1 chu_io_map.h and chu_io_map.svh 237</p> <p>10.4.2 inttypes.h 238</p> <p>10.4.3 chu_io_rw.h 239</p> <p>10.5 Techniques for low-level I/O operations 241</p> <p>10.5.1 Bit manipulation 241</p> <p>10.5.2 Packing and unpacking 242</p> <p>10.6 Device Drivers 243</p> <p>10.6.1 Overview 243</p> <p>10.6.2 GPO and GPI drivers 243</p> <p>10.6.3 Timer driver 245</p> <p>10.6.4 UART driver 247</p> <p>10.7 FPro utility routines and directory structure 248</p> <p>10.7.1 Minimal hardware requirements 248</p> <p>10.7.2 Utility routines 248</p> <p>10.7.3 Directory structure 251</p> <p>10.8 Test program 252</p> <p>10.8.1 IP core verification routine 252</p> <p>10.8.2 Programming with limited memory 252</p> <p>10.8.3 Test function integration 252</p> <p>10.8.4 Test program for the vanilla FPro system 253</p> <p>10.8.5 Implementation 254</p> <p>10.9 Bibliographic notes 255</p> <p>10.10 Suggested experiments 255</p> <p>10.10.1 Chasing LEDs 255</p> <p>10.10.2 Collision LEDs 256</p> <p>10.10.3 Pulse width modulation 256</p> <p>10.10.4 System time display 256</p> <p><b>11 FPro Bus Protocol and MMIO Slot Specification 257</b></p> <p>11.1 FPro bus 257</p> <p>11.1.1 Overview of the bus 257</p> <p>11.1.2 SoC interconnect 258</p> <p>11.1.3 FPro bus protocol specification 259</p> <p>11.2 Interface with the bus 260</p> <p>11.2.1 Introduction 260</p> <p>11.2.2 Write interface and decoding 261</p> <p>11.2.3 Read interface and multiplexing 263</p> <p>11.2.4 FIFO buffer as an I/O register 264</p> <p>11.2.5 Timing consideration 265</p> <p>11.3 MMIO I/O core 266</p> <p>11.3.1 MMIO slot interface specification 266</p> <p>11.3.2 Basic MMIO I/O core construction 268</p> <p>11.3.3 GPO and GPI cores 269</p> <p>11.4 Timer core development 270</p> <p>11.4.1 Custom logic 270</p> <p>11.4.2 Register map 271</p> <p>11.4.3 Wrapping circuit for the slot interface 271</p> <p>11.5 MMIO controller 272</p> <p>11.5.1 chu_io_map.svh file 273</p> <p>11.5.2 HDL code 273</p> <p>11.5.3 Vanilla MMIO subsystem 275</p> <p>11.6 MCS I/O bus and bridge 278</p> <p>11.6.1 Overview of Xilinx MicroBlaze MCS 278</p> <p>11.6.2 MicroBlaze MCS I/O bus 278</p> <p>11.6.3 MCS-to-FPro bridge 279</p> <p>11.7 Vanilla FPro system construction 281</p> <p>11.8 Bibliographic notes 282</p> <p>11.9 Suggested experiments 283</p> <p>11.9.1 FPro bus with a byte-lane enable signal 283</p> <p>11.9.2 Seven-segment control with a GPO core 283</p> <p>11.9.3 GPIO core 283</p> <p>11.9.4 Blinking-LED core 284</p> <p>11.9.5 Timer core with a programmable period 284</p> <p>11.9.6 Timer core with a run-once mode 284</p> <p><b>12 UART Core 287</b></p> <p>12.1 Introduction 287</p> <p>12.1.1 Overview of serial communication 287</p> <p>12.1.2 Overview of the UART 288</p> <p>12.1.3 Oversampling procedure 288</p> <p>12.2 UART construction 289</p> <p>12.2.1 Conceptual design 289</p> <p>12.2.2 Baud rate generator 290</p> <p>12.2.3 UART receiver 291</p> <p>12.2.4 UART transmitter 293</p> <p>12.2.5 Top-level HDL code 295</p> <p>12.3 UART core development 296</p> <p>12.3.1 Register map 296</p> <p>12.3.2 Wrapping circuit for the slot interface 297</p> <p>12.4 UART driver 298</p> <p>12.4.1 Class definition 299</p> <p>12.4.2 Basic methods 300</p> <p>12.4.3 ASCII code 301</p> <p>12.4.4 Display methods 303</p> <p>12.4.5 Test 305</p> <p>12.5 Additional project ideas 305</p> <p>12.5.1 Original serial port 305</p> <p>12.5.2 Emulated serial port 305</p> <p>12.5.3 Direct connection 306</p> <p>12.5.4 USB-to-UART adaptor 306</p> <p>12.5.5 Wireless adaptor 307</p> <p>12.6 Bibliographic notes 308</p> <p>12.7 Suggested experiments 308</p> <p>12.7.1 UART-controlled chasing LEDs 308</p> <p>12.7.2 Alternative read configuration 308</p> <p>12.7.3 UART controller with a parity bit 308</p> <p>12.7.4 UART core with an error status 309</p> <p>12.7.5 Configurable UART core 309</p> <p>12.7.6 UART core with automatic baud rate detection 309</p> <p>12.7.7 UART core with enhanced automatic baud rate detection 310</p> <p>12.7.8 UART core with an automatic baud rate and a parity detection circuit 310</p> <p><b>PART III EMBEDDED SOC II: BASIC I/O CORES</b></p> <p><b>13 Xilinx XADC Core 313</b></p> <p>13.1 Overview of XADC 313</p> <p>13.1.1 Block diagram 313</p> <p>13.1.2 Configuration 314</p> <p>13.2 XADC core development 315</p> <p>13.2.1 XADC instantiation 315</p> <p>13.2.2 Basic wrapping circuit design 316</p> <p>13.2.3 Register map 318</p> <p>13.2.4 HDL code 318</p> <p>13.3 XADC core device driver 320</p> <p>13.3.1 Class definition 320</p> <p>13.3.2 Class implementation 321</p> <p>13.3.3 Testing for the XADC core 322</p> <p>13.4 Sampler FPro system 323</p> <p>13.4.1 Testing procedure of an FPro core 323</p> <p>13.4.2 System configuration 323</p> <p>13.4.3 Hardware derivation 324</p> <p>13.4.4 Software verification program 331</p> <p>13.5 Additional project ideas 332</p> <p>13.6 Bibliographic notes 333</p> <p>13.7 Suggested experiments 333</p> <p>13.7.1 Real-time voltage display 333</p> <p>13.7.2 Potentiometer-controlled chasing LEDs 333</p> <p>13.7.3 Potentiometer-controlled LED dimmer 333</p> <p>13.7.4 Enhanced wrapping circuit: part I 333</p> <p>13.7.5 Enhanced wrapping circuit: part II 333</p> <p><b>14 Pulse Width Modulation Core 335</b></p> <p>14.1 Introduction 335</p> <p>14.1.1 PWM as analog output 335</p> <p>14.1.2 Main characteristics 336</p> <p>14.2 PWM design 336</p> <p>14.2.1 Basic design 336</p> <p>14.2.2 Enhanced design 337</p> <p>14.3 PWM core development 339</p> <p>14.3.1 Register map 339</p> <p>14.3.2 Wrapped PWM circuit 340</p> <p>14.4 PWM driver 341</p> <p>14.4.1 Class definition 341</p> <p>14.4.2 Class implementation 342</p> <p>14.5 Testing 343</p> <p>14.6 Project ideas 343</p> <p>14.7 Suggested experiments 345</p> <p>14.7.1 Police dash light 345</p> <p>14.7.2 Rainbow night light 345</p> <p>14.7.3 Enhanced PWM core: part I 345</p> <p>14.7.4 Enhanced PWM core: part II 346</p> <p>14.7.5 Enhanced GPIO core 346</p> <p>14.7.6 Servo motor driver 346</p> <p><b>15 Debouncing Core and LED-Mux Core 347</b></p> <p>15.1 Debouncing Core 347</p> <p>15.1.1 Multi-bit debouncing circuit 347</p> <p>15.1.2 Register map and the slot wrapping circuit 350</p> <p>15.1.3 Driver 351</p> <p>15.1.4 Test 352</p> <p>15.2 LED-mux core 352</p> <p>15.2.1 Eight-digit seven-segment LED display multiplexing circuit 352</p> <p>15.2.2 Register map and the slot wrapping circuit 354</p> <p>15.2.3 Driver 355</p> <p>15.2.4 Test 358</p> <p>15.3 Project ideas 358</p> <p>15.4 Suggested experiments 360</p> <p>15.4.1 Area comparison of two debouncing circuits 360</p> <p>15.4.2 Enhanced debouncing core: part I 360</p> <p>15.4.3 Enhanced debouncing core: part II 360</p> <p>15.4.4 Rotating square pattern revisited 360</p> <p>15.4.5 Heartbeat pattern revisited 360</p> <p>15.4.6 Stopwatch 360</p> <p>15.4.7 Enhanced LED-mux core 361</p> <p><b>16 SPI Core 363</b></p> <p>16.1 Overview 363</p> <p>16.1.1 Conceptual architecture 364</p> <p>16.1.2 Multiple-device configuration 364</p> <p>16.1.3 Basic timing 366</p> <p>16.1.4 Operation modes 367</p> <p>16.1.5 Undefined aspects 368</p> <p>16.2 SPI controller 369</p> <p>16.2.1 Basic design 369</p> <p>16.2.2 FSMD construction 370</p> <p>16.2.3 HDL implementation 370</p> <p>16.3 SPI core development 374</p> <p>16.3.1 Register map 374</p> <p>16.3.2 Wrapping circuit for the slot interface 374</p> <p>16.4 SPI driver 376</p> <p>16.4.1 Class definition 376</p> <p>16.4.2 Class implementation 377</p> <p>16.5 Test 378</p> <p>16.5.1 ADXL362 accelerometer 378</p> <p>16.5.2 Test program 380</p> <p>16.6 Project ideas 381</p> <p>16.6.1 SD card 381</p> <p>16.6.2 TFT LCD module 382</p> <p>16.7 Bibliographic notes 382</p> <p>16.8 Suggested experiments 382</p> <p>16.8.1 Inclination sensing 382</p> <p>16.8.2 “Tapping” detection 382</p> <p>16.8.3 ADXL362 C++ class 383</p> <p>16.8.4 Enhanced SPI controller: part I 383</p> <p>16.8.5 Enhanced SPI controller: part II 383</p> <p>16.8.6 “Automatic-read” ADXL362 wrapper: part I 383</p> <p>16.8.7 “Automatic-read” ADXL362 wrapper: part II 384</p> <p>16.8.8 Flash memory access 384</p> <p>16.8.9 SPI slave controller: part I 384</p> <p>16.8.10 SPI slave controller: part II 385</p> <p><b>17 </b>I<sup>2</sup>C<b> Core 387</b></p> <p>17.1 Overview 387</p> <p>17.1.1 Electrical characteristics 388</p> <p>17.1.2 Basic bus protocol 388</p> <p>17.1.3 Basic timing 389</p> <p>17.1.4 Additional features 390</p> <p>17.2 I<sup>2</sup>C controller 391</p> <p>17.2.1 Basic design 391</p> <p>17.2.2 Conceptual FSMD construction 391</p> <p>17.2.3 Output control logic 394</p> <p>17.2.4 I<sup>2</sup>C bus clock generation 394</p> <p>17.2.5 HDL implementation 395</p> <p>17.3 I<sup>2</sup>C core development 400</p> <p>17.3.1 Register map 400</p> <p>17.3.2 Wrapping circuit for the slot interface 400</p> <p>17.4 I<sup>2</sup>C driver 401</p> <p>17.4.1 Class definition 401</p> <p>17.4.2 Class implementation 402</p> <p>17.5 Test 405</p> <p>17.5.1 ADT7420 temperature sensor 405</p> <p>17.5.2 Test program 406</p> <p>17.6 Project idea 406</p> <p>17.7 Bibliographic notes 407</p> <p>17.8 Suggested experiments 407</p> <p>17.8.1 Thermometer 407</p> <p>17.8.2 ADT7420 C++ class 407</p> <p>17.8.3 Enhanced I<sup>2</sup>C core 408</p> <p>17.8.4 “Automatic-read” ADT7420 wrapper 408</p> <p>17.8.5 I<sup>2</sup>C slave controller: part I 408</p> <p>17.8.6 I<sup>2</sup>C slave controller: part II 408</p> <p><b>18 PS2 Core 409</b></p> <p>18.1 Introduction 409</p> <p>18.1.1 PS2-device-to-host communication protocol and timing 410</p> <p>18.1.2 Host-to-PS2-device communication protocol and timing 410</p> <p>18.2 PS2 controller 411</p> <p>18.2.1 Conceptual design 411</p> <p>18.2.2 PS2 receiving subsystem 411</p> <p>18.2.3 PS2 transmitting subsystem 415</p> <p>18.2.4 Complete PS2 system 419</p> <p>18.3 PS2 core development 420</p> <p>18.3.1 Register map 420</p> <p>18.3.2 Wrapping circuit for the slot interface 421</p> <p>18.4 PS2 driver 422</p> <p>18.4.1 Class definition 422</p> <p>18.4.2 Lower layer methods 422</p> <p>18.4.3 PS2 initialization routine 423</p> <p>18.4.4 Keyboard routine 425</p> <p>18.4.5 Mouse routine 428</p> <p>18.5 Test 430</p> <p>18.6 Bibliographic notes 431</p> <p>18.7 Suggested experiments 431</p> <p>18.7.1 PS2 receiving subsystem with watchdog timer 431</p> <p>18.7.2 Keyboard-controlled LED flashing circuit 432</p> <p>18.7.3 Enhanced keyboard driver routine: part I 432</p> <p>18.7.4 Enhanced keyboard driver routine: part II 432</p> <p>18.7.5 Remote-mode mouse driver 432</p> <p>18.7.6 Scroll-wheel mouse driver 432</p> <p><b>19 Sound I: DDFS Core 433</b></p> <p>19.1 Introduction 433</p> <p>19.2 Design and implementation 434</p> <p>19.2.1 Direct synthesis of a digital waveform 434</p> <p>19.2.2 Direct synthesis of an unmodulated analog waveform 435</p> <p>19.2.3 Direct synthesis of a modulated analog waveform 436</p> <p>19.3 Fixed-point arithmetic 437</p> <p>19.4 DDFS construction 438</p> <p>19.5 DAC (digital-to-analog converter) 440</p> <p>19.5.1 Conceptual design 440</p> <p>19.5.2 HDL implementation 441</p> <p>19.6 DDFS core development 442</p> <p>19.6.1 Register map 442</p> <p>19.6.2 Wrapping circuit for the slot interface 443</p> <p>19.7 DDFS driver 444</p> <p>19.7.1 Class definition 444</p> <p>19.7.2 Class implementation 445</p> <p>19.8 Test 447</p> <p>19.9 Bibliographic notes 448</p> <p>19.10 Suggested experiments 448</p> <p>19.10.1 Quadrature phase carrier generation 448</p> <p>19.10.2 Reduced-size phase-to-amplitude lookup table 448</p> <p>19.10.3 Additive harmonic synthesis 449</p> <p>19.10.4 Simple function generator 449</p> <p>19.10.5 Arbitrary waveform generator 449</p> <p>19.10.6 Sample-based synthesis 449</p> <p><b>20 Sound II: ADSR Core 451</b></p> <p>20.1 Introduction 451</p> <p>20.2 ADSR envelope generator 452</p> <p>20.2.1 Conceptual FSMD design 453</p> <p>20.2.2 ASMD chart 453</p> <p>20.2.3 HDL implementation 455</p> <p>20.3 ADSR core development 457</p> <p>20.3.1 Register map 457</p> <p>20.3.2 Wrapped ADSR circuit 458</p> <p>20.4 ADSR driver 460</p> <p>20.4.1 Class definition 460</p> <p>20.4.2 Configuration methods 461</p> <p>20.4.3 calc note freq() method 463</p> <p>20.4.4 play note() method 465</p> <p>20.5 Test 465</p> <p>20.6 Project idea 466</p> <p>20.7 Bibliographic notes 467</p> <p>20.8 Suggested experiments 467</p> <p>20.8.1 RTTTL music player 467</p> <p>20.8.2 ADSR envelope testing 467</p> <p>20.8.3 Pushbutton piano 467</p> <p>20.8.4 Keyboard piano 468</p> <p>20.8.5 Keyboard recorder 468</p> <p>20.8.6 Real-time mode ADSR generator 468</p> <p>20.8.7 Real-time mode pushbutton piano 468</p> <p>20.8.8 Merged DDFS and ADSR core 468</p> <p>20.8.9 ADSR core with an automatic play FIFO buffer 468</p> <p>20.8.10 ADSR core for frequency modulation 468</p> <p><b>PART IV EMBEDDED SOC III: VIDEO CORES</b></p> <p><b>21 Introduction to the Video System 471</b></p> <p>21.1 Introduction to a video display 471</p> <p>21.1.1 Conceptual video display 471</p> <p>21.1.2 VGA interface 472</p> <p>21.2 Stream interface 473</p> <p>21.2.1 Random-access interface versus stream interface 473</p> <p>21.2.2 Flow control of the stream interface 473</p> <p>21.3 VGA synchronization 475</p> <p>21.3.1 Basic operation of a CRT monitor 475</p> <p>21.3.2 Horizontal synchronization 476</p> <p>21.3.3 Vertical synchronization 478</p> <p>21.3.4 Pixel clock rate 479</p> <p>21.3.5 VGA synchronization circuit 480</p> <p>21.4 Bar test-pattern generator 483</p> <p>21.5 Color-to-grayscale conversion circuit 485</p> <p>21.6 Demo video system 486</p> <p>21.7 Advanced video standards 488</p> <p>21.8 Bibliographic notes 489</p> <p>21.9 Suggested experiments 489</p> <p>21.9.1 Horizontal bar test-pattern generator 489</p> <p>21.9.2 Color channel selection circuit 489</p> <p>21.9.3 Enhanced color-to-grayscale conversion circuit 489</p> <p>21.9.4 Square test-pattern generator: part I 489</p> <p>21.9.5 Square test-pattern generator: part II 489</p> <p>21.9.6 Square test-pattern generator: part III 490</p> <p>21.9.7 Square test-pattern generator: part IV 490</p> <p><b>22 FPro Video Subsystem 491</b></p> <p>22.1 Organization of the video subsystem 491</p> <p>22.1.1 Overview 491</p> <p>22.1.2 Video controller 493</p> <p>22.1.3 HDL of the video controller 494</p> <p>22.2 FPro video IP core 495</p> <p>22.2.1 Basic functionality 495</p> <p>22.2.2 Blending operation 496</p> <p>22.2.3 Core architecture 498</p> <p>22.2.4 Alternative core partition 500</p> <p>22.3 Example video cores 500</p> <p>22.3.1 Bar test-pattern generator core 500</p> <p>22.3.2 Color-to-grayscale conversion core 503</p> <p>22.3.3 “Dummy” core 504</p> <p>22.4 FPro video synchronization core 504</p> <p>22.4.1 Line buffer 505</p> <p>22.4.2 Enhanced video synchronization circuit 508</p> <p>22.4.3 HDL code 511</p> <p>22.5 Daisy video subsystem 512</p> <p>22.5.1 Subsystem overview 512</p> <p>22.5.2 Interface to the video synchronization core 513</p> <p>22.5.3 HDL code 513</p> <p>22.5.4 Timing and performance considerations 517</p> <p>22.6 Vanilla daisy FPro system 517</p> <p>22.6.1 Clock management core 518</p> <p>22.6.2 Updated chu_io_map.svh 519</p> <p>22.6.3 HDL code 519</p> <p>22.7 Video driver and test program 521</p> <p>22.7.1 Updated chu_io_map.h and chu_io_rw.h files 521</p> <p>22.7.2 GPV core driver 522</p> <p>22.7.3 Test program 523</p> <p>22.8 Bibliographic notes 524</p> <p>22.9 Suggested experiments 525</p> <p>22.9.1 Color channel selection core 525</p> <p>22.9.2 Enhanced color-to-grayscale conversion core 525</p> <p>22.9.3 Square test-pattern generator core 525</p> <p>22.9.4 Alpha blending circuit 525</p> <p>22.9.5 “Highlight” core 525</p> <p>22.9.6 SVGA synchronization core 526</p> <p>22.9.7 Configurable video synchronization core 526</p> <p>22.9.8 Pipelined video subsystem 526</p> <p><b>23 Sprite Core 527</b></p> <p>23.1 Introduction 527</p> <p>23.2 Basic design 528</p> <p>23.2.1 Sprite RAM 528</p> <p>23.2.2 In-region comparison circuit 529</p> <p>23.3 Mouse pointer core 530</p> <p>23.3.1 Pointer sprite RAM 530</p> <p>23.3.2 Pixel generation circuit 531</p> <p>23.3.3 Top-level design 532</p> <p>23.4 “Ghost” character core 534</p> <p>23.4.1 Multiple images and animation 534</p> <p>23.4.2 Overview of the palette scheme 535</p> <p>23.4.3 Ghost sprite RAM and the palette circuit 535</p> <p>23.4.4 Animation timing circuit 537</p> <p>23.4.5 Pixel generation circuit 537</p> <p>23.4.6 Top-level design 540</p> <p>23.5 Sprite core driver and test program 541</p> <p>23.5.1 Sprite core driver 541</p> <p>23.5.2 Test program 543</p> <p>23.6 Bibliographic notes 544</p> <p>23.7 Suggested experiments 544</p> <p>23.7.1 Mouse pointer control with PS2 core 544</p> <p>23.7.2 Emulated ghost core 544</p> <p>23.7.3 Palette circuit for the mouse pointer sprite 544</p> <p>23.7.4 Sprite scaling circuit 544</p> <p>23.7.5 Portrait mode display 545</p> <p>23.7.6 Multiple-object generation 545</p> <p>23.7.7 Animation speed control 545</p> <p>23.7.8 Imitated blinking LED: part I 545</p> <p>23.7.9 Imitated blinking LED: part II 545</p> <p>23.7.10 Imitated blinking LED: part III 546</p> <p><b>24 On-Screen-Display Core 547</b></p> <p>24.1 Introduction to tile graphics 547</p> <p>24.2 Basic OSD design 549</p> <p>24.2.1 Text-mode display 549</p> <p>24.2.2 Font ROM 550</p> <p>24.2.3 Tile RAM 550</p> <p>24.2.4 Basic organization 551</p> <p>24.3 OSD core 552</p> <p>24.3.1 Font ROM 552</p> <p>24.3.2 Pixel generation circuit 553</p> <p>24.3.3 Top-level design 555</p> <p>24.4 OSD core driver and test program 557</p> <p>24.4.1 OSD core driver 557</p> <p>24.4.2 Testing program 558</p> <p>24.5 Bibliographic notes 559</p> <p>24.6 Suggested experiments 559</p> <p>24.6.1 Rotating banner 559</p> <p>24.6.2 Text console 559</p> <p>24.6.3 Underline for the cursor 559</p> <p>24.6.4 Portrait-mode display 560</p> <p>24.6.5 Font scaling circuit: part I 560</p> <p>24.6.6 Font scaling circuit: part II 560</p> <p>24.6.7 Extended font 560</p> <p>24.6.8 Tile-based ghost core 560</p> <p><b>25 VGA Frame Buffer Core 561</b></p> <p>25.1 Overview 561</p> <p>25.2 Frame buffer core 562</p> <p>25.2.1 FPGA memory consideration 562</p> <p>25.2.2 Video memory module 562</p> <p>25.2.3 Address translation 563</p> <p>25.2.4 Pixel generation circuit 564</p> <p>25.2.5 Register map 566</p> <p>25.2.6 Top-level HDL code 566</p> <p>25.3 Driver and test program 567</p> <p>25.3.1 Frame buffer core driver 567</p> <p>25.3.2 Geometrical modeling 568</p> <p>25.3.3 Test program 570</p> <p>25.4 Project ideas 570</p> <p>25.5 Bibliographic notes 572</p> <p>25.6 Suggested experiments 572</p> <p>25.6.1 Virtual prototyping board panel 572</p> <p>25.6.2 Virtual analog wall clock 572</p> <p>25.6.3 Geometrical model functions 572</p> <p>25.6.4 Simulated “Etch a Sketch” toy 572</p> <p>25.6.5 Frame buffer core with 3-bit color depth 573</p> <p>25.6.6 Frame buffer core with 1-bit color depth 573</p> <p>25.6.7 QVGA frame buffer core 573</p> <p>25.6.8 Line drawing hardware accelerator 573</p> <p>25.6.9 Bidirectional frame buffer access: part I 573</p> <p>25.6.10 Bidirectional frame buffer access: part II 573</p> <p><b>PART V EPILOGUE</b></p> <p><b>26 What’s Next 577</b></p> <p>References 581</p> <p>Appendix A: Tutorials 585</p> <p>A.1 Overview of Xilinx Vivado IDE 585</p> <p>A.2 Short tutorial on Vivado hardware development 589</p> <p>A.2.1 Create a design project 590</p> <p>A.2.2 Add or create Xilinx IP core instances 591</p> <p>A.2.3 Add or create HDL design files 591</p> <p>A.2.4 Add a constraint file 592</p> <p>A.2.5 Perform synthesis, implementation, and bitstream generation 593</p> <p>A.2.6 Program an FPGA device 593</p> <p>A.3 Short tutorial on Vivado simulation 594</p> <p>A.3.1 Add or create HDL testbench 596</p> <p>A.3.2 Perform initial simulation 596</p> <p>A.3.3 Customize waveform display 597</p> <p>A.4 Tutorial on IP instantiation 597</p> <p>A.4.1 Dual-clock FIFO core via HDL templates 598</p> <p>A.4.2 IP Catalog utility 599</p> <p>A.4.3 Generate a MicroBlaze MCS component 600</p> <p>A.4.4 XADC IP core 601</p> <p>A.4.5 Clock management IP core 602</p> <p>A.5 Short tutorial on FPro system development 604</p> <p>A.5.1 Derive FPro system hardware 605</p> <p>A.5.2 Export hardware configuration 605</p> <p>A.5.3 Derive software 605</p> <p>A.5.4 Embed elf file into FPGA’s memory module and regenerate bitstream 608</p> <p>A.5.5 Set up the terminal emulator program 610</p> <p>A.5.6 Program an FPGA device 610</p> <p>A.6 Bibliographic notes 611</p> <p>Topic Index 613</p>
<p><b>PONG P. CHU, PhD</b> is an Associate Professor in the Department of Electrical Engineering and Computer Science at Cleveland State University, Cleveland, Ohio. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and has received multiple instructional grants from the National Science Foundation.
<p>A hands-on introduction to FPGA prototyping and SoC design <p>This is the successor edition of the popular FPGA Prototyping by Verilog Examples book. It follows the same "learning-by-doing" approach to teach the fundamentals and practices of HDL synthesis and FPGA prototyping. The new edition uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register-transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow the strict design guidelines and coding practices used for large, complex digital systems. <p>The book is completely updated and uses the SystemVerilog language, which "absorbs" the Verilog language. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software "programmability" and develop complex and interesting embedded system projects. The new edition <ul> <li> Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I<sup>2</sup>C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.</li> <li> Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.</li> <li> Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.</li> <li> Provides a detailed discussion on blocking and nonblocking statements and coding styles.</li> <li> Describes basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.</li> <li> Provides an overview of bus interconnect and interface circuit.</li> <li> Presents basic embedded system software development.</li> <li> Suggests additional modules and peripherals for interesting and challenging projects.</li> </ul> <p>FPGA Prototyping by SystemVerilog Examples makes a natural companion text for introductory and advanced digital design courses and embedded system courses. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

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